The Joint Electron Device Engineering Council (JEDEC) Solid State Technology Association specifies the standards for double data rate (DDR) synchronous dynamic random-access memories (SDRAMs) and definitions of the signaling protocol for the exchange of data between a memory controller of a host computer and a DDR-compatible memory module. The fourth-generation DDR (DDR4) SDRAM provides a maximum power-saving mode to improve energy efficiency compared to earlier generation DDR memories such as third-generation DDR (DDR3) SDRAM.
The DDR4 memory has primarily three power states, namely, a normal power state, a low power state, and a deep low power state. FIG. 1 is a simplified power state diagram of a DDR4 memory. The normal power state 101 corresponds to a power state of the DDR memory under normal operations. The low power state 111 is used to transition the power state of the DDR4 memory from an idle mode (i.e., the normal power state) to a precharge power down mode or an active power down mode. The deep low power state 121 is used to transition the power state of the DDR4 memory from the idle mode to a self-refresh mode or a max-power down mode. The low power state 111 has faster entries and exits, and the deep low power state 121 has slower entries and exits. Typically, a memory controller of a host computer manages the transition between power states using DDR4 commands and specified timings.
FIG. 2 shows a detailed power state diagram for a DDR4 memory. The idle state 212 is defined as a state where all banks of the DDR memory are closed, no data bursts are in progress, the clock enable (CKE) is high, and all timings from previous operations are satisfied. During a power-down, if all banks of the DDR memory are closed after any in-progress commands are completed, the DDR4 memory enters the precharge power-down mode 211 by an enter power-down (PDE) command and exits the precharge power-down mode 211 by an exit power-down (PDX) command. Both the PDE command and the PDX command are issued by a memory controller of a host computer.
The maximum power down mode 216 provides the lowest power mode. The DDR memory can enter the maximum power-down mode 216 from the idle state 212 via a mode register set (MRS) command and exit the maximum power-down mode 216 via a self-refresh exit (SRX) command followed by a no operation (NOP) command. Both the MRS command and the SRX command with NOP are issued by the memory controller of the host computer. In the maximum power down mode 216, the DDR4 memory may still maintain data retention but may not respond to any external host command except a maximum power saving mode exit command (i.e., the SRX command with NOP). Since the DDR4 memory does not respond to any external host command in the maximum power down mode 216, the max power down mode 216 is also referred to as a hibernate mode.
The DDR4 memory periodically refreshes a whole memory rank by entering the self-refresh mode 215 via a refresh command. For example, the DDR4 memory can enter the self-refresh mode 215 from the idle state 212 via a self-refresh entry (SRE) and exit to the idle mode 212 via a self-refresh exit (SRX). Both the SRE command and the SRX command are issued by the memory controller of the host computer. The self-refresh mode 215 can be entered only from the idle state 212.
After receiving a bank activate command prior to issuing a read or write command, the DDR4 memory enters the bank active mode 217 via transitioning from the idle state 212 through an activating state 213. A precharge command is used to deactivate the open row in a particular bank or the open row in all banks from the bank active state 217. Once a bank is precharged, the DDR4 memory is returned to the idle state 212 through a precharging state 214. The DDR4 memory must be reactivated prior to a read or write commands being issued to the bank. According to the DDR4 specification, a read request includes an ACT command for activating the bank and loading the row to a row buffer and a RD command following the ACT command for reading a column from the row buffer. To access another row, the memory controller needs to send a PRE command to precharge the bank for restoring the bank. Until a PRE command is received, the bank can stay in the bank active mode 217 even when the memory controller does not service any column reads or writes. When the memory module is in the bank active mode 217 having at least one activated bank but not servicing any request, the memory controller can issue a PDE command to make the bank enter the active power-down mode 218 to power down the bank.
The current DDR4 power schema has certain limitations. For example, there are only three primary power states, i.e., the normal power state, the low power state, and the deep low power state. A direct transition between the low power state and the deep low power state is not available as the transition between the low power state and the deep low power state must go through the normal power state. Furthermore, the entire process for power state transition is managed by a memory controller of a host computer.